1. Field
This invention relates, in general, to nonvolatile semiconductor memory devices and, more particularly, to NAND flash memory device having an architecture with a reduced bit-line loading, and a method of programming such a device.
2. Description
Semiconductor memories are classified into volatile semiconductor memories and non-volatile semiconductor memories. In the volatile semiconductor memories, data are stored and can be read out as long as the power is applied, and are lost when the power is turned off. On the other hand, non-volatile memories such as an MROM (MASK ROM), a PROM (Programmable ROM), an EPROM (Erasable and Programmable ROM), and an EEPROM (Electrically Erasable and Programmable ROM), and Flash memories are capable of storing data even with the power turned off.
Of these devices, flash memories are classified into NOR-type flash memories and NAND-type flash memories according to a connection structure of a cell and a bitline. The NOR-type flash memory can be easily adapted to high-speed operation, but has a disadvantage when it comes to providing a high degree of integration. In contrast, the NAND-type flash memory is advantageous when it comes to providing a high degree of integration.
FIGS. 1A and 1B illustrate, respectively, an initial state and a programmed state of a flash memory cell transistor having a floating gate.
As shown in FIGS. 1A-B, a single transistor-type flash memory cell 100 generally comprises: a channel formed between a source 105 and a drain 110 on a semiconductor substrate 115; a control gate 120; and a floating gate 130 formed between a dielectric oxide 140 and a gate oxide 150, where dielectric oxide 140, floating gate 130, gate oxide 150, and control gate 120 are stacked on the channel. Floating gate 130 traps electrons, and the trapped electrons are used to establish the threshold voltage of flash memory cell 100. The electrons moving to floating gate 130 are generated by Fowler-Nordheim tunneling (FN), electron injection, etc. Electron injection may be performed by channel hot-electron injection (CHE), channel-initiated secondary electron injection (CISEI), etc. Also, Fowler-Nordheim tunneling (FN) is generally used in flash memory devices for erasing data all at once. Further, when the nonvolatile semiconductor memory device performs a read operation, the data value stored in flash memory cell 100 is determined through sensing the threshold voltage of flash memory cell 100, as discussed in further detail below.
As shown in FIG. 1A, initially flash memory cell 100 is in a “non-programmed” (or “erased”) state and stores a logical “1” therein. In the non-programmed state, flash memory cell 100 has an initial threshold voltage, VTH1, such that when a voltage less than VTH1 is applied to control gate 120, flash memory cell 100 is turned off, but when a voltage greater than VTH1 is applied to control gate 120, flash memory cell 100 is turned on. VTH1 is typically from −1V to −3V.
Meanwhile, as shown in FIG. 1B, flash memory cell 100 stores a logical “0” when it is in a “programmed” state. In the programmed state, memory cell 100 has an initial threshold voltage, VTH2 greater than VTH1, such that when a voltage less than VTH2 is applied to control gate 120, flash memory cell 100 is turned off, but when a voltage greater than VTH2 is applied to control gate 120, flash memory cell 100 is turned on. VTH2 is typically from +1V to +3V.
FIGS. 2A and 2B illustrate, respectively an erase operation and a programming operation for flash memory cell 100.
As seen in FIG. 2A, an erase operation is performed on flash memory cell 100 to store logical a “1” therein by applying an erase voltage “VERASE” to the bulk substrate 115 of flash memory cell 100 and grounding control gate 120 to thereby remove electrons from memory cell 100's floating gate 130. Removing electrons from floating gate 130 reduces the threshold voltage of flash memory cell 100 to VTH1. In a typical example, threshold voltage VTH1, may be distributed from −1V to −3V. After the erase operation is performed on flash memory cell 100, it is referred to as an “Erased Cell”, and it stores a logical “1.” In general, the erase voltage VERASE is greater than an operating voltage VCC of the NAND flash memory device. For instance, the erase voltage could be 19V while operating voltage VCC is only 5V.
As seen in FIG. 2B, a programming operation is performed on flash memory cell 100 to store a logical ‘0’ therein by applying a program voltage VPGM to control gate 120 of flash memory cell 110, and causing current to flow source 105 and drain 110 to thereby cause electrons in the current to be stored in floating gate 130. Storing electrons in floating gate 130 increases the threshold voltage of flash memory cell 100 to VTH2>VTH1. In a typical example, threshold voltage VTH2 may be distributed from +1V to +3V. After the programming operation is performed on flash memory cell 100, it is referred to as a “Programmed Cell”, and it stores a logical “0.”
FIG. 3 illustrates the architecture of a basic NAND flash memory device 300, comprising a memory cell array 320, a plurality (m) of row decoders 340, a page buffer block 360, and a column decoder 380. Memory cell array 320 comprises a plurality of memory blocks 325. Each memory block 325 comprises a plurality (k+1) of memory cell strings (“strings”) each connected to a corresponding bit line 330. In turn, each bit line 330 is connected to a plurality of strings—one string in each memory block 325. Page buffer block 360 includes a plurality of page buffers.
FIG. 4 illustrates the organization of memory block 400 of a basic NAND flash memory cell array, and an associated page buffer block 450 including a plurality of page buffers PB0 through PBz. As seen in FIG. 3, in general a memory cell array comprises a number (m) of such memory blocks 400, with the size of the array being defined by the block size multiplied by the number of memory blocks; i.e., ((n+1)*(k+1))*m. Two bit lines are connected to each page buffer PBi, which has a selection means to switch between the two (even and odd) bit lines. Page buffer block 450 loads data onto the bit lines during a data programming operation, and during a data read operation page buffer block 450 latches and senses data transferred onto the bit lines. The memory cells connected to one word line define a page of memory cells.
FIG. 5 illustrates in more detail a basic NAND flash memory cell array including a plurality of NAND flash memory cell strings (“strings”) 500 connected to bit lines BL0 through BLk, respectively. Each string 500 comprises a string select transistor (SST), a ground select transistor (GST), and a plurality of flash memory cells 100 serially connected between string selection transistor SST and ground select transistor GST. Typically, either 16 or 32 flash memory cells 100 are serially connected in flash memory cell string 500. String select transistor SST has a drain connected to a corresponding bit line and a gate connected to a string select line SSL. Memory cells 100 are connected to corresponding word lines WL0 through WLn, respectively. Ground select transistor (GST) has a drain connected to a cell source line (CSL). Word lines WL0 through WLn, string select line SSL, and ground select line GSL are driven by a row decoder circuit (see FIG. 3).
In order to program the memory cells of a selected row (or word line) of a NAND flash memory device, the memory cells in a memory block are first erased in order to give each memory cell the threshold voltage VTH1 that is less than 0V (all memory cells store a logical “1.”). Once the memory cells are erased, program data is loaded onto the page buffers of the NAND flash memory device, and then a high voltage pump circuit generates relatively high voltage programming pulses for a programming operation. Afterward, the loaded data is programmed into the memory cells of a selected word line by the iteration of program loops including a sequence of programming pulses. Each of the program loops consists of a bit line setup interval, a program interval, a discharge/recovery interval, and a verification interval.
During the bit line setup interval, each of the bit lines BL0 through BLk is charged to a power supply voltage or a ground voltage in accordance with the loaded program data. That is, a bit line BL connected to a memory cell to be programmed with a “0” is charged to the ground voltage, and a bit line BL connected to a memory cell to be program inhibited (i.e., not programmed) so as to remain storing a logical “1” is charged to the power supply voltage. Within the program interval, the program voltage VPGM is supplied to a selected word line and the pass voltage VPASS is supplied to the unselected word lines. For memory cells connected to the selected word line and to bit lines that are charged to the ground voltage, a bias condition great enough to induce F-N tunneling is satisfied, so electrons are injected from the bulk to the floating gates of the memory cells. On the other hand, as is well known in the art, memory cells connected to bit lines that are charged to the power supply voltage are program inhibited. The voltages of the bit lines and the word lines are discharged during the discharge interval, which functions as a recovery interval, and whether the memory cells have reached a target threshold voltage is determined during the verification interval.
FIG. 6 shows the voltage conditions for various operations of a NAND flash memory cell array.
FIG. 7 is a more detailed diagram showing the arrangement of a bit line and a plurality of associated strings in a memory device. As can be seen in FIGS. 5 and 7, each string is connected to a bit line through a string select transistor, and the bit line in turn is connected to a page buffer. The bit line itself has no serially connected transistors or switches between the page buffer and the string select transistor SST.
However, this arrangement has some drawbacks. Since all of the blocks are connected to each bitline, as the number of blocks increase, the loading on the bitline also increases, slowing down an operational speed of the memory device. Also, only one memory cell connected to one word line can be programmed at one time among all of the word lines of all of the blocks connected to each bitline. So the speed of programming the memory device decreases as more memory blocks are connected to a bit line to increase the storage capacity of the memory device.
Accordingly, it would be desirable to provide a NAND flash memory device with a reduced bitline load. It would also be desirable to provide a NAND flash memory device which can be programmed more rapidly. Other and further objects and advantages will appear hereinafter.
The present invention comprises a nonvolatile semiconductor memory with low-loading bit line architecture and a method of programming the same.
In one aspect of the invention, a NAND flash memory device comprises: an array of NAND flash memory cells; a plurality of word lines connected to the NAND flash memory cells; and a plurality of bit lines connected to the NAND flash memory cells. The bit lines each comprise, a first bit line portion, a second bit line portion, and a switching device extending between the first and second bit line portions to selectively connect the first and second bit line portions together. At least a first NAND flash memory cell is connected to the first bit line portion, and at least a second NAND flash memory cell is connected to the second bit line portion.
In another aspect of the invention, a method is provided for programming the NAND flash memory cells of a NAND flash memory device comprising an array of NAND flash memory cells arranged in a plurality of word lines and a plurality of bit lines, the bit lines each comprising a first bit line portion, a second bit line portion, and a switching device extending between the first and second bit line portions to selectively connect the first and second bit line portions, and further comprising a first page buffer connected to the first bit line portions and a second page buffer connected to the second bit line portions. The method of programming the NAND flash memory cells comprises: loading into the primary page buffer second data to be programmed into second NAND flash memory cells connected to the second bit line portions; transferring the second data from the primary page buffer to the secondary page buffer; loading into the primary page buffer first data to be programmed into first NAND flash memory cells connected to the first bit line portions; controlling the switching devices to disconnect the first and second portions of the bit lines from each other; and programming the first NAND flash memory cells with the first data of the primary page buffer while programming the second NAND flash memory cells with the second data of the secondary page buffer.